A conventional temperature compensated ECL differential output gate with cutoff driver circuit is illustrated in FIG. 1. The basic ECL output gate, also referred to herein as an ECL gate and an ECL differential gate, is provided by the gate transistor elements Q5 and Q6. In this example gate transistor element Q5 provides a direct input transistor element for receiving ECL logic input signals of ECL logic high and low potential levels at the direct input SX. Gate transistor element Q6 provides an inverted input transistor element to which an ECL logic inverted input signal is applied at the inverted signal input SXN. Alternatively gate transistor element Q6 may provide a reference transistor element to which a reference voltage signal is applied at an intermediate reference voltage level between the ECL logic input signal high and low potential levels. Either arrangement is referred to herein as an ECL gate, ECL differential gate or ECL output gate.
The emitter nodes of ECL gate transistors Q5 and Q6 are coupled together at a common emitter node coupling E1. Current sink I1 is coupled in a circuit between the common emitter node coupling E1 and the ECL low potential power rail designated V.sub.EE. The voltage level of the low potential power rail V.sub.EE is typically -4.2 v to -4.8 v. In the example of FIG. 1 the output enable gate transistor element Q7 and resistor element R4 are coupled between the ECL gate common emitter node coupling E1 and current sink I1 effectively forming a cutoff current sink switch as hereafter described.
The current sink I1 is provided by a current source transistor element Q13 with a tail resistor element R5 in its emitter current path for generating the sink current or tail current. A bias voltage generator, not shown, provides the current source voltage V.sub.CS applied to the base of the current source transistor element Q13 of the current sink I1. The current source voltage level V.sub.CS is selected typically to be for example, 1.32 v above the low potential power rail V.sub.EE.
The ECL differential gate transistor elements Q5 and Q6 provide alternative current paths through respective collector path swing voltage resistor elements R1 and R2 which are in turn coupled to the ECL high potential power rail V.sub.CC. The ECL high potential power rail V.sub.CC is, for example, at ground potential 0v, also designated GND. Typically the swing voltage resistor elements R1 and R2 have substantially equal resistance. Current sink I1 generates the ECL differential gate current in one of the alternative current paths through either of the swing resistor elements R1 or R2 according to the differential input signals at the complementary inputs SX and SXN at the respective base nodes of ECL gate transistor elements Q5 and Q6.
As further shown in FIG. 1 the ECL gate differential or complementary output signals are derived from the respective collector nodes of ECL gate transistor elements Q5 and Q6. The collector nodes are output switching nodes which provide output signals of high and low potential through respective output buffer emitter follower transistor elements Q1 and Q4 at the respective differential and complementary outputs QXN and QX. The collector node of ECL gate transistor element Q6 through output buffer emitter follower transistor element Q4 provides the true output signal QX for an input signal SX at the base node of gate transistor element Q5. Conversely, the collector node of gate transistor element Q5 through output buffer emitter follower transistor element Q1 provides the inverted output signal QXN for an inverted input signal SXN at the base node of gate transistor element Q6.
Output buffer emitter follower transistor elements Q1 and Q4 are coupled respectively at the collector nodes to a separate ECL high potential power rail or output power rail V.sub.CCA. The external or output high potential power rail V.sub.CCA may be relatively isolated from the internal high potential power rail V.sub.CC to isolate the internal circuits from power rail noise perturbations on the output power rails due to switching events on the common bus. The emitter terminals of emitter follower transistor elements Q1 and Q4 are also typically terminated through respective terminating resistors RT at terminating voltage level V.sub.TT of, for example, -2.0 v. The ECL logic high and low potential levels at complementary outputs QX and QXN are therefore established between the ground potential 0 v at the ECL high potential power rail V.sub.CC and the terminating voltage -2.0 v at the terminating voltage source V.sub.TT according to the voltage drop and voltage swing across swing resistors R1 and R2. This is in turn set by the size of the swing resistors and of the sink current generated by current sink Il.
The conventional cutoff driver circuit for the ECL output gate is provided by, in this example, first and second output enable (OE) differential gates. The first OE differential gate includes the OE transistor element Q12 and cutoff transistor elements Q10 and Q11 all coupled together at a common emitter node coupling E2. A second current sink I2 is coupled between the common emitter node coupling E2 of the OE differential gate transistor elements Q10, Q11 and Q12 and the ECL low potential power rail V.sub.EE. Current sink I2 is provided by current source transistor element Q14 and tail resistor R6. The current source voltage V.sub.CS provides the base drive for the current source transistor element Q14. An output enable input signal OE is applied at the base node of OE transistor element Q12 while the complementary or inverted output enable signal OEN is applied at the base nodes of cutoff transistor elements Q10 and Q11.
The collector terminal of OE transistor element Q12 is coupled directly to the ECL high potential power rail V.sub.CC for supplying current sink I2 when OE transistor element Q12 is conducting during normal switching mode operation. The collector node of one of the cutoff transistor elements Q10 is coupled to swing resistor R1 at the collector node of ECL gate input transistor element Q5, while the collector node of the other cutoff transistor element Q11 is coupled to the swing resistor element R2 at the collector node of the ECL gate complementary input transistor element Q6. In this way the voltage drop across swing resistor elements R1 and R2 may be increased by the tail current generated by current sink I2 when cutoff transistor elements Q10 and Q11 are conducting in the cutoff state.
The second OE differential gate is provided by OE transistor element Q7 and cutoff transistor elements Q8 and Q9 coupled together at a third common emitter node coupling E3. The first current sink I1 is coupled between the common emitter node coupling E3 of OE differential gate transistor elements Q7, Q8 and Q9 and the low potential power rail V.sub.EE. The output enable input signal OE is applied at the base node of OE transistor element Q7 while the complementary or inverse output enable signal OEN is applied at the common base node coupling of cutoff transistor elements Q8 and Q9. In this manner when cutoff transistor elements Q8 and Q9 are conducting, the voltage drop across swing resistor elements R1 and R2 may be increased by the sink current or tail current generated by current sink I1 when the cutoff transistor elements Q8 and Q9 are conducting in the cutoff state.
When OE transistor element Q7 is conducting the ECL gate current flows through either of the ECL gate transistor element collector paths defined by swing resistor elements R1 and R2. The current requirements of the first current sink I1 are therefore satisfied through the ECL gate. The OE transistor element Q7 in combination with parallel resistor element R4 provides an effective current switch between the first common emitter node coupling E1 of the ECL differential gate and the common emitter node coupling E3 of the second OE differential gate. When OE transistor element Q7 is not conducting the first current sink I1 is effectively disconnected from the ECL output gate.
During normal switching operation of the ECL output gate, the output enable input signal OE is at high potential and the OE transistor elements Q7 and Q12 are conducting. The complementary output enable signal OEN is at low potential and the cutoff transistor elements Q8, Q9, Q10 and Q11 are off. OE transistor element Q12 satisfies the tail current requirements for current sink I2 while OE transistor element Q7 connects current sink I1 to the ECL output gate for normal switching operation between ECL logic high and low potential levels at the complementary inputs SX and SXN and the complementary outputs QX and QXN.
For the cutoff state, the output enable signal OE is at low potential and the complementary output enable signal OEN is at high potential. As a result OE transistor elements Q7 and Q12 are relatively non-conducting while the cutoff transistor elements Q8, Q9, Q10 and Q11 are conducting current through swing resistor elements R1 and R2 in order to satisfy the relatively large current requirements of current sinks I1 and I2.
The total sinking current of current sinks I1 and I2 is therefore forced through the swing resistor elements or load resistor elements R1 and R2. The abnormally large current causes a large voltage drop across swing resistor elements R1 and R2. The output voltage level at the respective emitter node ECL outputs QXN and QX of output buffer emitter follower transistor elements Q1 and Q4 is shifted down to a cutoff potential level V.sub.OLZ below the ECL logic signal low potential level V.sub.OL and approaching the load termination voltage V.sub.TT of, e.g. -2.0 v. The complementary ECL outputs QX and QXN are therefore held at the cutoff potential level V.sub.OLZ analogous to the high impedance third state, for applications with multiple ECL output gates on a common bus.
One disadvantage of the conventional ECL output gate cutoff driver circuit is that the temperature compensation for the ECL logic high and low potential levels V.sub.OH and V.sub.OL operative during normal switching mode operation of the ECL gate is ineffective and inoperative during the cutoff state. Temperature compensation at the ECL gate is effected by the triplet circuit or crossover network provided by base collector shorted (BCS) diode transistor elements Q2 and Q3 and resistor element R3 coupled between the collector nodes of ECL gate transistor elements Q5 and Q6. The temperature compensating network Q2, Q3, R3 is operative over the desired temperature range for the ECL logic high and low potential levels V.sub.OH and V.sub.OL during normal switching mode operation when the current generated by current sink I2 flows through OE transistor element Q12. When the sinking current generated by current sink I2 flows through cutoff transistor elements Q10 and Q11 and swing resistor elements R1 and R2 during the cutoff state, temperature compensation is not achieved.
With increasing temperature, the negative temperature coefficient of the base emitter junctions cause V.sub.BE 's to decrease. This increases the sink current generated by the current sinks and in turn increases the voltage drop across the swing resistors R1 and R2. At hot temperatures the capacitance across all components increases also. In the non-cutoff state, that is in the normal switching mode operation of the ECL gate, the positive temperature coefficient of the swing resistors may substantially compensate for the negative temperature coefficient of the V.sub.BE 's as temperature increases.
In the cutoff state however the current through the ECL swing resistor elements R1 and R2 is exaggerated. The positive temperature coefficient of the resistors no longer provides substantial compensation at high temperature. The extra current, increasing the voltage drop across swing resistors R1 and R2 pulls down the outputs QX and QXN below the desired cutoff potential level V.sub.OLZ, of for example -1.95 v, to a deeper cutoff condition for example approaching the terminating voltage V.sub.TT. It therefore takes longer to return from the cutoff state to the normal switching mode operation range between V.sub.OL and V.sub.OH.
This problem presented by the prior art ECL gate cutoff driver circuit is a problem caused by operation of the circuit in the hot temperature operating range and in the cutoff state when there is additional current passing through the ECL gate swing resistor elements. Not only is there a delay in the start of transition from the cutoff state to a valid ECL logic high or low potential level but also a decrease in the slope of the transition for an overall total delay in both starting and switching, and a net slowdown in the operation of the ECL gate.
For a typical ECL gate coupled between the ECL high and low potential level power rails V.sub.CC and V.sub.EE as set forth above, the temperature compensated ECL logic high and low potential levels V.sub.OH and V.sub.OL are for example -0.95 v and -1.70 v respectively. The room temperature cutoff voltage level V.sub.OLZ, is set approximately at -1.95 v approaching the terminating voltage V.sub.TT of -2.0 v, but slightly above. As a result the emitter follower output buffer transistor elements Q1 and Q4 at room temperature are slightly on. This reduces propagation delay in return of the outputs QX and QXN from the cutoff potential level V.sub.OLZ in the cutoff state to one of the valid ECL logic high and low potential levels V.sub.OH, V.sub.OL in the switching mode. Without temperature compensation in the cutoff state however, the emitter follower output buffer transistor elements Q1 and Q4 may turnoff completely. The downward drift of V.sub.OLZ with increasing temperature poses no problem for the DC cutoff condition. But, for transient AC switching and return to the switching mode, undesirable propagation delay or "step out" is introduced in the high temperature operating range.
This undesirable delay in going from the cutoff state to high and low transitions at high temperature in comparison to room temperature is illustrated in FIG. 2. In this example the transition of the complementary output enable signal OEN from high potential in the cutoff state to low potential in the normal switching mode is followed by comparative transitions at the respective complementary outputs QX and QXN to ECL logic high and low potential levels. The transitions at the respective outputs QX and QXN are substantially delayed at high temperature in comparison to room temperature.